1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor integrated circuits, and more specifically to a method for forming interconnect and contacts to lower conducting layers, and the structures formed thereby.
2. Description of the Prior Art
In scaling down the dimensions of semiconductor integrated circuit structures, a severe limitation is encountered regarding the alignment of contact patterns and interconnections. Misalignment of the interconnect lead pattern with respect to the contact pattern can drastically reduce the actual contact area, which greatly increases contact resistance. In order to compensate for possible misalignment, the dimensions of the interconnect lines are typically enlarged at the contact location to ensure complete overlap with the contact opening even in the case of maximum misalignment. This reduces device density on the circuit.
Polycrystalline silicon is typically used for the lower levels of interconnect. Polycrystalline silicon is relatively stable during later high temperature processing steps, and bonds well to underlying layers. However, the use of polycrystalline silicon does have some drawbacks. Even if it is heavily doped with impurities, the resistivity of polycrystalline silicon is usually too high to be useful as a conductive interconnetion layer. This problem is usually overcome by forming a refractory metal silicide layer over the polycrystalline silicon. This silicide layer has a relatively low resistivity, and becomes the primary path for current flow through the interconnect layer.
Although interconnection resistance is reduced by silicidation of the polycrystalline silicon interconnect, processing complexities are increased due to the requirement of etching both the silicide layer and the underlying polycrystalline silicon when defining the interconnect signal leads. Such etching of the two layer film is, in general, more difficult than etching a single film type such as polycrystalline silicon.
Another problem with the standard approach to interconnect silicidation is that the actual contact between the interconnect layer and the underlying substrate or lower interconnect layer is made only by the polycrystalline silicon in the upper interconnect layer. Thus, the resistivity of the polycrystalline silicon increases the resistance of the contact. In addition, a thin layer of oxide tends to grow on the exposed silicon in the bottom of the contact opening before the overlying polycrystalline silicon layer is deposited. When a metal is deposited directly in a contact, recombination of the oxygen with the metal tends to minimize the contact resistance. Unlike the deposition of a metal in a contact, deposition of the overlying polycrystalline silicon layer does not tend to remove this thin oxide layer. Thus, contact resistances tend to be higher than resistances caused by the remaining portions of the interconnect layer.
An additional problem that must be considered when depositing polycrystalline silicon over a contact is that a rectifying P-N junction is formed if the conductivity types of the two conductive layers are not the same. In some instances this junction may not be harmful, but in most cases a true ohmic contact is required. In CMOS circuits, wherein a single interconnect lead must make contact to both P-type and N-type substrates, additional measures must be undertaken to ensure that no rectifying junctions are formed. For example, one approach is to dope the interconnect layer with both P-type and N-type impurities, with the appropriate types being located near the appropriate contacts, and strapping the entire interconnect layer with a metal silicide layer. This causes the junction, formed only in the interconnect layer, to be shorted by the silicide layer, but introduces additional complexity and mask steps into the production process.
It would be desirable to provide a technique for forming integrated circuits which addresses the various problems described above. It would be desirable to provide a method and structure which minimizes interconnect resistance, contact resistance, and alignment considerations.